1. Field of the Invention
The present invention relates to a method of making bonded wafers of SOI type with a thermally grown oxide layer sandwiched therebetween (hereinafter merely referred to as bonded wafers and SOI is an abbreviation of Silicon-on-Insulator.) .
2. Description of the Prior Art
A substrate for use in semiconductor device fabrication is required increasingly to have a higher degree of freedom in designing of a devise fabricated thereon. Therefore, this trend of requirement makes the substrate of so-called SOI type to draw more attention to itself, which is bonded wafers being structured such that a thermally grown oxide layer sandwiched between two silicon wafers and at least one of them is monocrystalline. The bonded wafer may be in use for making an electronic device such as a semiconductor device or, for example, micro machine in one of the other fields of application.
In general, a conventional method of the bonded wafer comprises the steps of at least one of two mirror-polished wafers being thermally oxidized and thereby forming a silicon oxide layer all over the surface, superposing the two wafers, one on the other and with the silicon oxide layer sandwiched therebetween, bonding the wafers firmly by applying heat treatment to the thus superposed wafers, and finally grinding and polishing the thermally oxidized wafer (hereinafter referred to as a bond wafer) to make it a thin layer with a mirror-like surface thereon.
The thus made bonded wafers often have chances to separate from each other due to poor bonding even in the thinning step of the bond wafer and somewhere in a following device fabrication process.
In order to increase the bonding strength of bonded wafers the above mentioned heat treatment is usually carried out at a high temperature selected in the range more than 1000.degree. C. The heat treatment at a high temperature in the range does not have a problem in the case where the both wafers do not have a diffused layer therein since the redistribution of an impurity by thermal diffusion is not a matter for deep reflection.
As for wafers, for instance, in which lateral concentrated impurity (as dopant) layers are introduced or impurity diffused regions are patterned, the high temperature heat treatment for bonding the wafers invites the problem of redistribution of an impurity by thermal diffusion.
On the other hand, the advantages peculiar to the bonded wafers draws recent attentions in not a few fields of application of an electronics-related technology. Taking examples, the SOI type bonded wafers with an ultra-thin bond wafer has been obtained by means of so-called the etch stop method, wherein, for example, the characteristic relation in regard to KOH etching rate vs boron concentration for monocrystalline silicon is utilized to stop a KOH etching of the bond wafer at a high boron concentration in the vicinity of the bonding interface and thereby to leave the very thin bond wafer. Furthermore, fabrication of three dimensional integrated circuits is within the bounds of possibility.
In order to bring a reality to these applications, it is absolutely necessary that a relatively lower temperature range is adopted in the heat treatment so as not to induce an impurity redistribution and that to realize the bonding strength large enough.
A method to realize the necessities above mentioned is proposed, which is to apply an electrostatic force between wafers superposed.
According to the method, however, electrodes have to be mounted, therefore it lacks ability of mass production and what's more the applied electrical field has a chance to deteriorate the quality of the oxide layer interposed in the bonded wafers.